VHDL Simili 2.2 Release Notes

The second generation of our ZEro-Overhead-Stack (ZEOS-II) technology is introduced in 3.0. The benefits of this simulation kernel implementation result in up to 8x performance improvement over release 2.3 for the Professional Edition. The Standard Edition also features significant kernel performance improvement over release 2.3.
The Professional Edition contains enhancements that are performed by concurrently analyzing the entire design hierarchy -- also termed global optimizations. This results in much higher simulation performance.
The Professional Edition also benefits from new optimizations for VHDL Vital Level 1 architectures. Most compilers/simulators do not optimize Level 1 architectures.

Resolution Control

You can now control the simulator resolution to achieve faster simulations. For instance, your gate level simulations can run twice as fast if you set the simulator resolution to nanoseconds ("1ns") instead of picoseconds ("1ps"). The default resolution is "1ps" for 3.0. In release 2.3, the simulator was fixed at femtosecond resolution ("1fs"), which is typically much higher resolution than the signal switching rates observable in a real-world design.

Sonata GUI Enhancements

Our fast and efficient waveform viewer gets even faster. Performance of viewing analog waveforms has been enhanced. Zooming and scaling analog waveforms is responsive even with a large number of analog waveforms.
In Sonata's Simulator settings dialog box, you can now disable SDF annotation. In release 2.3, you had to delete the entry and then re-enter from scratch when needed. You can now simply enable/disable each SDF annotation entry.
In the language-sensitive Text Editor, the character font is now user selectable.
On the Linux platform, you can now select your favorite HTML browser (default is Mozilla). On Windows, Sonata always uses the browser registered to handle HTML files.