VHDL Simili Documentation:

Simulator (vhdle):

Once all the required models are compiled, the next task is to simulate. In VHDL, you must select a top level entity (with an optional architecture) or a configuration to simulate. The process of simulation is preceded by a process of elaboration. Elaboration can be seen simply as a preparation step for simulation. In VHDL Simili, the process of elaboration and simulation occurs in one step using the command vhdle (elaboration is transparent).

Currently, vhdle is a batch program that runs without any user intervention. It has no mechanism (like some of the other simulators) to enter stimulus. We recommend the test-bench methodology for creating stimulus (and optionally to also check the results). You can use the full power of VHDL to create stimulus to drive the inputs, or even use VHDL file-IO to read/write test vectors from an external file. The simulation process automatically terminates when all activity ceases in the simulation model. VHDL Simili provides a facility for monitoring signals at any level in your design hierarchy using a command file. Please refer to the command file reference for more information.

Command line summary:

vhdle supports a multitude of options. Most of these options are for advanced use. The following is a very simplified command summary

vhdle [options] top-level-design-unit

Assuming your top level entity name is myentity (in the work library), use the following command:

vhdle myentity

This will start the simulation of the myentity VHDL entity using the most recently compiled architecture for it. If you would like to simulate a particular architecture(say myarch) of myentity, use the following command:

vhdle myentity(myarch)

You can also use a configuration as your top level. Assuming you have a configuration named myconfig, use the following command line:

vhdle myconfig

Simulator options:

The options listed below can help you control the behavior of the simulator. Note that certain options require arguments and certain arguments are optional. Optional items are specified using square brackets "[]" and a choice is separated by the character '|'.

-h

Prints a summary of all the available options with some examples.

-s

Enables silent mode. Most messages are suppressed.

-work library-name

You can use this option to override the default library (work). You will need this option if your top level model is in a non-work library. For example, the following command:

vhdle -work mylib myentity

will allow you to simulate the model "myentity" from the library "mylib".

-ini initialization-file-name

You can use this option to override the default INI file name used to setup library associations. When this option is not specified, a search is done to find the file "symphony.ini" in the current working directory first and then in the installation directory. You can use this option to specify any file to be read as an INI file (as long as the file has the expected format). See Introduction for more information on the INI file. Hint: You can use the Sonata project file (.sws file) as an INI file since it uses the same format as the INI file. It is an error if this option is specified but file could not be opened for reading.

-p

This option will suppress the printing of progress messages to the screen during simulation. When this option is disabled, the current simulation time is not printed onto the screen (normally, this occurs at least once a second).

-gName=Value

Using this option, you can override values for generics for the top level architecture/entity. Note that this option is invalid if your top level design is a configuration. Using this option, you can override all scalar type generics (integers, enums, reals and physicals) and 1-dimensional character type arrays (such as bit_vector, std_logic_vector, string, etc.). Quotes are optional for arrays (double quotes) and enumerated (single quotes) types. Also, case is significant for the array and enumerated character literals. The generic name itself is treated in a case-insensitive manner. For numeric arguments, simple decimal constants are recommended although for integers and reals, based literals are also allowed. For physical literals (such as time), only decimal literals can optionally precede the physical unit name and the physical unit name is required.

vhdle -gMyInt=32 -gMyTime=10.0ns -gMyReal=20.0 -gMyStr=hello myentity

vhdle -gMyStr=" this string has spaces " myentity

If the generic that is being set already has a default value (implicit or explicit), it will be never be evaluated and will be replaced by the one supplied by this option.

Note that spaces are not allowed unless they are enclosed in quotes.

-GName=Value

Using this option, you can override values for generics at any level of the hierarchy. This option is very similar to the '-g' option described above except that it can be used as a global override to override generics at all levels of the hierarchy.

-do command-file

Once the design is loaded into the simulator and elaborated, this command file specified by this option will be read. This options is primarily used to specify commands to monitor signals in your design and write the signal transitions to a simple text file. Please refer to the Command Reference Manual for more information about the syntax and features offered by such a command file. See examples below.

-list list-file

This option is used in conjunction with the -do command and is ignored if no -do command is specified. This option specifies the name of the file that is used when writing out the signal transitions. If this command is not specified, the default file name is "simili.lst" in the current directory.

vhdle myentity -t 1us -do simili.cmd
vhdle myentity -do simili.cmd -list run1.lst

The first command simulates myentity for 1us, reads the commands specified in the file "simili.cmd" and creates the output file "simili.lst". The second command is similar to the first one except that the simulation will run until there is nothing to simulate and uses the file "run1.lst" as the output file. Note that the ".lst" extension is not special and you can chose any extension you would like.

-t time[unit]

Runs the simulation for the given amount of time. Normally, simulation automatically terminates when all simulation activity ceases. However, if your test bench runs forever, you may need to use this option to limit the amount of time simulation is run. There valid time units are fs, ps, ns, us, ms, sec, hr and min. If unit is not specified, the default of fs is assumed. There must not be a space between the the "time" and the "unit". Following are some examples of specifying a maximum simulation time.

vhdle -t 10ns myentity   -- Run for 10 nanoseconds
vhdle -t 100us myentity  -- Run for 100 microseconds
vhdle -t 100 us myentity -- !!!NOT VALID!!!
vhdle -t 100 myentity    -- Run for 100 femtoseconds

-r time[unit]

The format of this option is similar to the "-t" option above and can be used to restrict the simulation resolution. This option is currently ignored.

-stdin filename

Use this option to redirect the INPUT file defined in standard package TEXTIO to be any user defined file. All read requests on the INPUT file are redirected to the file specified by "filename" (this file must exist).

-stdout filename

Use this option to redirect the OUTPUT file defined in standard package TEXTIO to be any user defined file. All write requests on the OUTPUT file are redirected to the file specified by "filename". Note that the contents of the file specified by "filename" are overwritten.

-sdf[min | typ | max] [InstancePath=]SdfFileName

The -sdf option can be used to specify SDF timing data with a particular instance. The -sdfmin uses the minimum values, the -sdfmax option uses the maximum values and the -sdftyp option uses the typical values from the SDF file. The -sdf (without a min, typ, max suffix) option implies typical values. The optional "InstancePath" identifies the exact instance to which the SDF back-annotation values apply to. If no InstancePath is given, or if the InstancePath of "/" is given, it implies the top level of the model. Note that you can use this option multiple times to back annotate data from several SDF files to the various instances of your model. The following applies the SDF file mysdf.sdf (typical values) to the instance "/u0/u1" of "myentity"

vhdle -sdf /u0/u1=mysdf.sdf myentity

The following is an example demonstrating the back-annotation of multiple SDF files.

vhdle -sdfmin /u0=musdf1.sdf -sdfmax /u1=mysdf2.sdf myentity

The following two examples are equivalent and the both apply to the top level "myentity".

vhdle -sdftyp /=mysdf.sdf myentity
vhdle -sdftyp mysdf.sdf myentity

Note: '/' represents a hierarchy separator
Note: Versions of SDF supporeted: 2.1, 3.0 and 4.0
Note: Versions of Vital supported: Vital95, Vital 3.0, IEEE 1076.4-Oct-95
Note: The "InstancePath" is case sensitive -- for normal VHDL instance names, please use lower case characters for instance path (unless you have extended identifiers in your path)

-noaccel name

To improve simulation performance, many of the industry standard VHDL packages have been accelerated. Using this option you can disable acceleration for a given type of VHDL package. The argument for -noaccel must be one of 1164, std_logic_arith, numeric_bit, numeric_std, vital or ALL. 'ALL' disables all package accelerations. 1164 disables acceleration for the IEEE std_logic_1164 package. std_logic_arith disables acceleration for synopsys libraries (std_logic_arith and related packages). You can specify this option multiple times to disable more than one package(s). Note: Disabling acceleration can lead to extremely slow simulations.

-nowarn name

This option relates to the -noaccel mentioned above. The numeric_bit and numeric_std packages offer a compile time constant that determines whether or not warnings should be printed under certain circumstances. By default, these warnings are enabled. When using the accelerated versions of these packages, disable these warnings. This option has no effect if you are using un-accelerated versions of these packages. The 'name' has to be one of numeric_bit, numeric_std, std_logic_arith or ALL. You can specify this option multiple times. Please note that disabling these warnings may hide important bugs in your design. In a lot of cases, you can eliminate these warnings by simply initializing your variables/signals. The -nowarn option does not have any effect if acceleration has been disabled for the package.

-nocycleopt

VHDL Simili uses some special optimizations to accelerate simulations. However, under rare circumstances, simulation results may differ from other VHDL simulators with respect to the exact delta cycle in which a given signal is updated. You can disable this kind of optimization using this option. We recommend not using this option unless you are very particular as to the exact delta cycle at which your signals are updated.

-breakon severity

'severity' can be NOTE, WARNING, ERROR or FAILURE. By default, the simulation stops when a FAILURE (via an ASSERT or a REPORT statement) is detected by the model being simulated. However, there might be instances where you might want to stop the simulation for ASSERT/REPORT's of a lower severity. Use this option to make the simulation stop at a different severity level.

Exit code:

The exit code is 0 if there were no errors and non-zero otherwise. This might be helpful for scripts/makefiles checking for a successful run.

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