Symphony EDA Customer Support -- Tech Note #3
Problem with universal integers, also problems with multiplying a real value with the result of a division of two physical values
Applies to: VHDL Simili Version 1.4/1.5/2.0
VHDL has an anonymous predefined type called "universal integer" along with a named type called "INTEGER". There is a very subtle difference between the two. A "universal integer" can be implicitly type converted to any integer type (including INTEGER) but an "INTEGER" type does not convert to other integer types without an explicit type-conversion. In VHDL Simili 1.4/1.5, there is no concept of a "universal integer" (or "universal real") as a separate type. In most cases, you will not miss this subtle omission. However, it has come to our notice that this has caused certain incompatibilities or resulted in legal VHDL being declared illegal by the compiler.
The problem most often occurs when the result of a division of two physical values is used to multiply with a real number. Consider the following assignment (myrealvalue is of type REAL)...
The sub-expression (1 ps / 1 fs) produces a universal-integer in a compliant compiler but in VHDL Simili, it produces an "INTEGER" type. Also, since there is no operator ("*") defined to multiply a real (in particular a "universal real" with an INTEGER, this results in the compiler not being able to find the appropriate operator. A compliant compiler would have done the following type reduction/resolution to the expression on the right-hand-side above...
And since there is a function defined to multiply a universal-real with a universal-integer in the std.standard package, the above three transformations would have occurred properly. However, VHDL Simili does the following.
Note however that integer constants are effectively treated as "universal integers" and real constants are also treated properly as "universal reals".
As a work around, you may have to use explicit type-conversions. For example, the above expression could have been written as follows to satisfy VHDL Simili
Although rare, this problem can also result from other scenarios but the workaround of using an explicit type conversion will still work.
PROCEDUREFor Version 2.0 or lower, use explicit type-conversions to work around this problem. This problem has been fixed in Version 2.1.
Send mail to
questions or comments about this web site.