Symphony EDA Customer Support -- Tech Note #2
Compiler produces false errors on enumeration literals that have the same name as a subprogram
Applies to: VHDL Simili Version 1.4
VHDL allows overloading in the case of subprogram names and enumeration literals. However, when VHDL Simili was designed it was not understood that an enumeration literal name could also be used as a subprogram name and vice-versa. VHDL Simili allows the same name to be used in multiple enumerated types and also supports subprogram overloading. However, it gets confused and produces false syntax errors when the same name is used as both an enumeration literal as well as a subprogram name. This deficiency has been remedied in Simili version 1.5 but since the changes required to support overloading correctly were so drastic, version 1.4 will continue to have this problem.
The following is an example which demonstrates this problem. In this example, the identifier WRITE and READ are defined in textio (as a subprogram) and another package (as an enum. literal).. When either the WRITE or READ are used while both are visible, the compiler either complain (the exact complaint may be different due to visibility rules).
Another example of this problem can be shown in the following code in a very different way. This example fails to compile because the compiler does not like the same name being used for an enum. literal and a subprogram name in the exact same declarative region.
PROCEDUREVHDL Simili 1.5 is contains the fix for this problem. The only workaround is to rename either the subprogram(s) or the enumeration literal(s) so that they do not overload each other.
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